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features applications description pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 low-voltage and low-power stereo audio digital-to-analog converter with lineout amplifier portable audio player multilevel dac including lineout amplifier cellular phone analog performance (v cc1 , v cc2 = 2.4 v): pda ? dynamic range: 98 db typ other applications requiring low-voltage ? thd+n at 0 db: 0.007% typ operation 1.6-v to 3.6-v single power supply low power dissipation: 6 mw at v cc1 , v cc2 = 2.4 v the pcm1772 and pcm1773 devices are cmos, system clock: 128 f s , 192 f s , 256 f s , 384 f s monolithic, integrated circuits which include stereo sampling frequency: 5 khz to 50 khz digital-to-analog converters, lineout circuitry, and support circuitry in small tssop-16 and vqfn-20 software control (pcm1772): packages. ? 16-, 20-, 24-bit word available the data converters use ti's enhanced multilevel d - s ? left-, right-justified, and i 2 s architecture, which employs noise shaping and ? slave/master selectable multilevel amplitude quantization to achieve excellent ? digital attenuation: 0 db to ?62 db, dynamic performance and improved tolerance to clock jitter. the pcm1772 and pcm1773 devices 1 db/step accept several industry standard audio data formats ? 44.1-khz digital de-emphasis with 16- to 24-bit data, left-justified, i 2 s, etc., ? zero cross attenuation providing easy interfacing to audio dsp and decoder ? digital soft mute devices. sampling rates up to 50 khz are supported. a full set of user-programmable functions is ? monaural analog-in with mixing accessible through a 3-wire serial control port, which ? monaural speaker mode supports register write functions. hardware control (pcm1773): ? left-justified and i 2 s ? 44.1-khz digital de-emphasis ? monaural analog-in with mixing pop-noise-free circuit 3.3-v tolerant packages: tssop-16 and vqfn-20 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2001?2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.

absolute maximum ratings recommended operating conditions pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. over operating free-air temperature range unless otherwise noted (1) pcm1772 pcm1773 supply voltage: v cc1 , v cc2 ?0.3 v to 4 v supply voltage differences: v cc1 , v cc2 0.1 v ground voltage differences 0.1 v digital input voltage ?0.3 v to 4 v input current (any terminals except supplies) 10 ma operating temperature ?40c to 125c storage temperature ?55c to 150c junction temperature 150c lead temperature (soldering) 260c, 5 s package temperature (ir reflow, peak) 260c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating free-air temperature range min nom max unit supply voltage: v cc 1, v cc 2 1.6 2.4 3.6 v digital input logic family cmos system clock 0.64 19.2 mhz digital input clock frequency sampling clock 5 50 khz analog output load resistance 10 k w analog input level (v cc 2 = 2.4 v) 1.4 vp-p operating free-air temperature, t a ?25 85 c 2 submit documentation feedback www.ti.com
electrical characteristics pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted pcm1772pw, pcm1773pw, pcm1772rga, pcm1773rga parameter test conditions unit min typ max resolution 24 bits operating frequency sampling frequency (f s ) 5 50 khz system clock frequency 128 f s , 192 f s , 256 f s , 384 f s digital input/output (1) (2) 0.7 v ih vdc v cc1 input logic level v il 0.3 v cc1 vdc i ih v in = v cc1 10 m a input logic current i il v in = 0 v ?10 m a 0.7 v oh i oh = ?2 ma vdc v cc1 output logic level (3) v ol i ol = 2 ma 0.3 v cc1 vdc dynamic performance (line output) full-scale output voltage 0 db 0.77 v cc2 v p-p dynamic range eiaj, a-weighted 90 98 db signal-to-noise ratio eiaj, a-weighted 90 98 db thd+n 0 db 0.007% 0.015% channel separation 70 80 db load resistance 10 k w dc accuracy gain error 2 8 % of fsr gain mismatch, 2 8 % of fsr channel-to-channel bipolar zero error v out = 0.5 v cc1 at bpz 30 75 mv analog line input (mixing circuit) analog input voltage range 0.584 v cc2 v p-p gain (analog input to line output) 0.91 analog input impedance 10 k w thd+n ain = 0.56 v cc2 (peak-to-peak) 0.1% digital filter performance pass band 0.454 f s stop band 0.546 f s pass-band ripple 0.04 db stop-band attenuation ?50 db group delay 20/f s 44.1-khz de-emphasis error 0.1 db analog filter performance frequency response at 20 khz 0.2 db (1) digital inputs and outputs are cmos compatible. (2) all logic inputs are 3.3-v tolerant and not terminated internally. (3) lrck and bck terminals 3 submit documentation feedback www.ti.com
pin assignments pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 electrical characteristics (continued) all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted pcm1772pw, pcm1773pw, pcm1772rga, pcm1773rga parameter test conditions unit min typ max power supply requirements voltage range, v cc1 , v cc2 1.6 2.4 3.6 vdc i cc1 bpz input 1.5 2.5 ma i cc2 supply current bpz input 1 2.5 i cc1 + i cc2 power down (4) 5 15 m a bpz input 6 12 mw power dissipation power down (4) 12 36 m w temperature range operation temperature ?25 85 c pcm1772pw, -73pw: 16-terminal tssop 150 q ja thermal resistance c/w pcm1772rga, -73rga: 20-terminal vqfn 130 (4) all input signals are held static. 4 submit documentation feedback www.ti.com 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 lrck data bck pd agnd1agnd2 v com v out r sckims mcmd v cc1 v cc2 ainv out l pcm1772 pw p ackage (t op view) 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 lrck data bck pd agnd1agnd2 v com v out r sckifmt amix demp v cc1 v cc2 ainv out l pcm1773 pw p ackage (t op view) p0001-01 pcm1772 rga p ackage (t op view) data bck pd agnd1agnd2 lrck nc nc nc scki com nc ain v r out v l out v nc no internal connection fmtamix demp v cc1 v cc2 pcm1773 rga p ackage (t op view) data bck pd agnd1agnd2 lrck nc nc nc scki com nc ain v ms mcmd v cc1 v cc2 12 3 4 5 1514 13 12 11 6 7 8 9 10 20 19 18 17 16 12 3 4 5 1514 13 12 11 6 7 8 9 10 20 19 18 17 16 r out v l out v p0002-01
terminal functions pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 pcm1772pw terminal i/o description name no. agnd1 5 ? analog ground. this is a return for v cc1 . agnd2 6 ? analog ground. this is a return for v cc2 . ain 10 i monaural analog signal mixer input. the signal can be mixed with the output of the l- and r-channel dacs. bck 3 i/o serial bit clock. clocks the individual bits of the audio data input, data. in the slave interface mode, this clock is input from an external device. in master interface mode, the pcm1772 device generates the bck output to an external device. data 2 i serial audio data input lrck 1 i/o left and right clock. determines which channel is being input on the audio data input, data. the frequency of lrck must be the same as the audio sampling rate. in the slave interface mode, this clock is input from an external device. in the master interface mode, the pcm1772 device generates the lrck output to an external device. mc 14 i mode control port serial bit clock input. clocks the individual bits of the control data input, md. md 13 i mode control port serial data input. controls the operation mode on the pcm1772 device. ms 15 i mode control port select. the control port is active when this terminal is low. pd 4 i reset input. when low, the pcm1772 device is powered down, and all mode control registers are reset to default settings. scki 16 i system clock input v cc1 12 ? power supply for all analog circuits except the lineout amplifier. v cc2 11 ? analog power supply for the lineout amplifier circuits. the voltage level must be the same as v cc1 . v com 7 ? decoupling capacitor connection. an external 10- m f capacitor connected from this terminal to analog ground is required for noise filtering. voltage level of this terminal is 0.5 v cc2 nominal. v out l 9 o l-channel analog signal output of the lineout amplifiers v out r 8 o r-channel analog signal output of the lineout amplifiers 5 submit documentation feedback www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 pcm1772rga terminal i/o description name no. agnd1 4 ? analog ground. this is a return for v cc1 . agnd2 5 ? analog ground. this is a return for v cc2 . ain 10 i monaural analog signal mixer input. the signal can be mixed with the output of the l- and r-channel dacs. bck 2 i/o serial bit clock. clocks the individual bits of the audio data input, data. in the slave interface mode, this clock is input from an external device. in the master interface mode, the pcm1772 device generates the bck output to an external device. data 1 i serial audio data input lrck 20 i/o left and right clock. determines which channel is being input on the audio data input, data. the frequency of lrck must be the same as the audio sampling rate. in the slave interface mode, this clock is input from an external device. in the master interface mode, the pcm1772 device generates the lrck output to an external device. mc 14 i mode control port serial bit clock input. clocks the individual bits of the control data input, md. md 13 i mode control port serial data input. controls the operation mode on the pcm1772 device. ms 15 i mode control port select. the control port is active when this terminal is low. nc 8, 17, ? no connect 18, 19 pd 3 i reset input. when low, the pcm1772 device is powered down, and all mode control registers are reset to default settings. scki 16 i system clock input v cc1 12 ? power supply for all analog circuits except lineout amplifier. v cc2 11 ? analog power supply for lineout amplifier circuits. the voltage level must be the same as v cc1 . v com 6 ? decoupling capacitor connection. an external 10- m f capacitor connected from this terminal to analog ground is required for noise filtering. voltage level of this terminal is 0.5 v cc2 nominal. v out l 9 o l-channel analog signal output of lineout amplifiers. v out r 7 o r-channel analog signal output of lineout amplifiers. 6 submit documentation feedback www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 pcm1773pw terminal i/o description name no. agnd1 5 ? analog ground. this is a return for v cc1 . agnd2 6 ? analog ground. this is a return for v cc2 . ain 10 i monaural analog signal mixer input. the signal can be mixed with the output of the l- and r-channel dacs. amix 14 i analog mixing control bck 3 i serial bit clock. clocks the individual bits of the audio data input, data. data 2 i serial audio data input demp 13 i de-emphasis control fmt 15 i data format select lrck 1 i left and right clock. determines which channel is being input on the audio data input, data. the frequency of lrck must be the same as the audio sampling rate. pd 4 i reset input. when low, the pcm1773 device is powered down, and all mode control registers are reset to default settings. scki 16 i system clock input v cc1 12 ? power supply for all analog circuits except the lineout amplifier v cc2 11 ? analog power supply for the lineout amplifier circuits. the voltage level must be the same as v cc1 . v com 7 ? decoupling capacitor connection. an external 10- m f capacitor connected from this terminal to analog ground is required for noise filtering. voltage level of this terminal is 0.5 v cc2 nominal. v out l 9 o l-channel analog signal output of the lineout amplifiers v out r 8 o r-channel analog signal output of the lineout amplifiers pcm1773rga terminal i/o description name no. agnd1 4 ? analog ground. this is a return for v cc1 . agnd2 5 ? analog ground. this is a return for v cc2 . ain 10 i monaural analog signal mixer input. the signal can be mixed with the output of the l- and r-channel dacs. amix 14 i analog mixing control bck 2 i serial bit clock. clocks the individual bits of the audio data input, data. data 1 i serial audio data input demp 13 i de-emphasis control fmt 15 i data format select lrck 20 i left and right clock. determines which channel is being input on the audio data input, data. the frequency of lrck must be the same as the audio sampling rate. nc 8, 17, ? no connect 18, 19 pd 3 i reset input. when low, the pcm1773 device is powered down, and all mode control registers are reset to default settings. scki 16 i system clock input v cc1 12 ? power supply for all analog circuits except the lineout amplifier v cc2 11 ? analog power supply for the lineout amplifier circuits. the voltage level must be the same as v cc1 . v com 6 ? decoupling capacitor connection. an external 10- m f capacitor connected from this terminal to analog ground is required for noise filtering. voltage level of this terminal is 0.5 v cc2 nominal. v out l 9 o l-channel analog signal output of the lineout amplifiers v out r 7 o r-channel analog signal output of the lineout amplifiers 7 submit documentation feedback www.ti.com
typical performance curves digital filter digital filter (de-emphasis off) pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 functional block diagram all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted. amplitude amplitude vs vs frequency frequency figure 1. figure 2. 8 submit documentation feedback www.ti.com dac ds audio interface 8 digital filter + dac ds spi port 8 digital filter + v com clock manager power supply lrck data bck (fmt) ms (amix) mc (demp) md scki pd v cc1 v cc2 v out r v com v out l ain digital attenuator lineout amplifier ( ) : pcm1773 agnd1 agnd2 b0001-01 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 1 2 3 4 amplitude db g001 f frequency [ f s ] f frequency [ f s ] ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0 0.1 0.2 0.3 0.4 0.5 amplitude db g002
de-emphasis curves pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 typical performance curves (continued) all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted. de-emphasis level de-emphasis error vs vs frequency frequency figure 3. figure 4. total harmonic distortion + noise dynamic range vs vs supply voltage supply voltage figure 5. figure 6. 9 submit documentation feedback www.ti.com f frequency [ f s ] ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 de-emphasis level db g003 f frequency khz ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 de-emphasis error db g004 0.01 0.10 1.00 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 v cc supply v oltage v thd+n t otal harmonic distortion + noise % 0.1 0.01 0.001 g005 v cc supply v oltage v 92 94 96 98 100 102 104 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 dynamic range db g006
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 typical performance curves (continued) all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted. signal-to-noise ratio channel separation vs vs supply voltage supply voltage figure 7. figure 8. total harmonic distortion + noise dynamic range vs vs free-air temperature free-air temperature figure 9. figure 10. 10 submit documentation feedback t a free-air t emperature c 94 95 96 97 98 99 100 101 102 ?40 ?20 0 20 40 60 80 100 dynamic range db g010 www.ti.com v cc supply v oltage v 74 76 78 80 82 84 86 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 channel separation db g008 v cc supply v oltage v 92 94 96 98 100 102 104 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 snr signal-to-noise ratio ? db g007 0.01 0.10 1.00 ?40 ?20 0 20 40 60 80 100 t a free-air t emperature c thd+n t otal harmonic distortion + noise % 0.1 0.01 0.001 g009
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 typical performance curves (continued) all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted. signal-to-noise ratio channel separation vs vs free-air temperature free-air temperature figure 11. figure 12. supply current supply current vs vs supply voltage sampling frequency figure 13. figure 14. 11 submit documentation feedback t a free-air t emperature c 94 95 96 97 98 99 100 101 102 ?40 ?20 0 20 40 60 80 100 snr signal-to-noise ratio ? db g011 t a free-air t emperature c 76 77 78 79 80 81 82 83 84 ?40 ?20 0 20 40 60 80 100 channel separation db g012 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 10 20 30 40 50 2018 16 14 12 10 8 6 4 2 0 f s sampling frequency khz i cc supply current, operational ma power down operational i cc supply current, power down m a g014 www.ti.com 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 i cc supply current, operational ma power down operational 2018 16 14 12 10 8 6 4 2 0 v cc supply current v i cc supply current, power down m a g013
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 typical performance curves (continued) all specifications at t a = 25c, v cc1 = v cc2 = 2.4 v, f s = 44.1 khz, system clock = 256 f s and 24-bit data, r l = 10 k w , unless otherwise noted. dynamic range vs jitter figure 15. output spectrum (?60 db, n = 8192) output spectrum (?60 db, n = 8192) figure 16. figure 17. 12 submit documentation feedback www.ti.com jitter ps 94 95 96 97 98 99 100 0 100 200 300 400 500 600 700 dynamic range db g015 f frequency khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 amplitude db g016 f frequency khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 80 100 120 amplitude db g017
detailed description system clock, reset, and functions system clock input pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the pcm1772 and pcm1773 devices require a system clock for operating the digital interpolation filters and multilevel d - s modulators. the system clock is applied at terminal 16 (scki). table 1 shows examples of system clock frequencies for common audio sampling rates. figure 18 shows the timing requirements for the system clock input. for optimal performance, it is important to use a clock source with low phase jitter and noise. table 1. system clock frequency for common audio sampling frequencies sampling frequency, lrck system clock frequency, scki (mhz) 128 f s 192 f s 256 f s 384 f s 48 khz 6.144 9.216 12.288 18.432 44.1 khz 5.6448 8.4672 11.2896 16.9344 32 khz 4.096 6.144 8.192 12.288 24 khz 3.072 4.608 6.144 9.216 22.05 khz 2.8224 4.2336 5.6448 8.4672 16 khz 2.048 3.072 4.096 6.144 12 khz 1.536 2.304 3.072 4.608 11.025 khz 1.4112 2.1168 2.8224 4.2336 8 khz 1.024 1.536 2.048 3.072 symbol parameter min unit t (sckh) system clock pulse duration, high 7 ns t (sckl) system clock pulse duration, low 7 ns t (scky) system clock pulse cycle time (1) 52 ns (1) 1/(128 f s ), 1/(192 f s ), 1/(256 f s ) or 1/(384 f s ) figure 18. system clock timing 13 submit documentation feedback www.ti.com t (sckh) t (scky) scki t (sckl) 0.7 v cc1 0.3 v cc1 t0005-01
power on/off and reset pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the pcm1772/73 always must have the pd pin set from low to high once after power-supply voltages v cc1 and v cc2 have reached the specified voltage range and stable clocks scki, bck, and lrck are being supplied for the power-on sequence. a minimum time of 1 ms after both the clock and power-supply requirements are met is required before the pd pin changes from low to high, as shown in figure 19 . subsequent to the pd low-to-high transition, the internal logic state is held in reset for 1024 system clock cycles prior to the start of the power-on sequence. during the power-on sequence, v out l and v out r increase gradually from ground level, reaching an output level that corresponds to the input data after a period of 9334/f s . when powering off, the pd pin is set from high to low first. then v out l and v out r decrease gradually to ground level over a period of 9334/f s , as shown in figure 20 , after which power can be removed without creating pop noise. when powering on or off, adhering to the timing requirements of figure 19 and figure 20 ensures that pop noise does not occur. if the timing requirements are not met, pop noise might occur. figure 19. power-on sequence figure 20. power-off sequence 14 submit documentation feedback www.ti.com v cc1 , v cc2 0 v lrck, bck, scki pd internal reset v out l, v out r 1024 internal system clocks 9334/f s 0 v 1 ms (min) 1 ms (min) t0006-01 v cc1 , v cc2 0 v lrck, bck, scki pd v out l, v out r 0 v 9334/f s t0007-01
power-up/-down sequence and reset pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the pcm1772 device has two kinds of power-up/-down methods: the pd terminal through hardware control and pwrd (register 4, b0) through software control. the pcm1773 device has only the pd terminal through hardware control for the power-up/-down sequence. the power-up or power-down sequence operates the same as the power-on or power-off sequence. when powering up or down using the pd terminal, all digital circuits are reset. when powering up or down using pwrd, all digital circuits are reset except for maintaining the logic states of the registers. figure 21 shows the power-up/power-down sequence. figure 21. power-down and power-up sequences 15 submit documentation feedback v cc1 , v cc2 2.4 v lrck, bck, scki pd v out l, v out r 9334/f s 9334/f s 0 v t0008-01 www.ti.com
audio serial interface audio data formats and timing pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the audio serial interface for the pcm1772 and pcm1773 devices consists of a 3-wire synchronous serial port. it includes terminals 1 (lrck), 2 (data), and 3 (bck). bck is the serial audio bit clock, and it clocks the serial data present on data into the audio interface serial shift register. serial data is clocked into the pcm1772 and pcm1773 devices on the rising edge of bck. lrck is the serial audio left/right word clock. it latches serial data into the serial audio interface internal registers. both lrck and bck of the pcm1772 device support the slave and master modes, which are set by fmt (register 3). lrck and bck are outputs during the master mode and inputs during the slave mode. in slave mode, bck and lrck are synchronous to the audio system clock, scki. ideally, it is recommended that lrck and bck be derived from scki. lrck is operated at the sampling frequency, f s . bck can be operated at 32, 48, and 64 times the sampling frequency. in master mode, bck and lrck are derived from the system clock, and these terminals are outputs. the bck and lrck are synchronous to scki. lrck is operated at the sampling frequency, f s . bck can be operated at 64 times the sampling frequency. the pcm1772 and pcm1773 devices operate under lrck, synchronized with the system clock. the pcm1772 and pcm1773 devices do not need a specific phase relationship between lrck and the system clock, but do require the synchronization of lrck and the system clock. if the relationship between the system clock and lrck changes more than 3 bck during one sample period, internal operation of the pcm1772 and pcm1773 devices halts within 1/f s , and the analog output is kept in last data until resynchronization between system clock and lrck is completed. the pcm1772 device supports industry-standard audio data formats, including standard, i 2 s, and left justified. the pcm1773 device supports the i 2 s and left-justified data formats. table 2 lists the main features of the audio data interface. figure 22 shows the data formats. data formats are selected using the format bits, fmt[2:0] of control register 3 in case of the pcm1772 device, and are selected using the fmt terminal in case of the pcm1773 device. the default data format is 24-bit, left-justified, slave mode. all formats require binary 2s complement, msb-first audio data. figure 23 shows a detailed timing diagram for the serial audio interface in slave mode. figure 24 shows a detailed timing diagram for the serial audio interface in master mode. table 2. audio data interface audio-data interface feature characteristic pcm1772 standard, i 2 s, left-justified audio data interface format pcm1773 i 2 s, left-justified audio data bit length 16-, 20-, 24-bit, selectable audio data format msb first, 2s complement 16 submit documentation feedback www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 figure 22. audio data input formats 17 submit documentation feedback (2) i 2 s data format; l-channel = low , r-channel = high (slave mode) lrck bck r-channel l-channel data 14 15 16 1 2 15 16 msb lsb 3 14 1 2 15 16 msb lsb 3 14 data 14 15 16 1 2 15 16 msb lsb 3 14 15 16 lsb 14 lrck bck r-channel l-channel data 1 2 n?1 n msb lsb 3 n?2 1 2 n?1 n msb lsb 3 n?2 1 2 1/f s (= 32 f s , 48 f s or 64 f s ) 16-bit right-justified, bck = 32 f s 16-bit right-justified, bck = 48 f s or 64 f s 1/f s (1) standard data format; l-channel = high, r-channel = low (slave mode) (3) left-justified data format; l-channel = high, r-channel = low (slave mode) data 18 19 20 1 2 19 20 msb lsb 3 18 1 2 19 20 msb lsb 3 18 20-bit right-justified data 22 23 24 1 2 23 24 msb lsb 3 22 1 2 23 24 msb lsb 3 22 24-bit right-justified 1 2 msb 3 lrck bck r-channel l-channel data 1 2 n?1 n msb lsb 3 n?2 1 2 n?1 n msb lsb 3 n?2 1 2 1/f s (= 32 f s , 48 f s or 64 f s ) (= 32 f s , 48 f s or 64 f s ) (4) left-justified data format; l-channel = high, r-channel = low (master mode) (the frequency of bck is 64 f s and scki is 256 f s only) lrck bck r-channel l-channel data 1 2 n?1 n msb lsb 3 n?2 1 2 n?1 n msb lsb 3 n?2 1 2 1/f s (= 64 f s ) t0009-01 www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 parameters symbol min max unit bck pulse cycle time t (bcy) 1/(64 f s ) (1) bck high-level time t (bch) 35 ns bck low-level time t (bcl) 35 ns bck rising edge to lrck edge t (bl) 10 ns lrck edge to bck rising edge t (lb) 10 ns data setup time t (ds) 10 ns data hold time t (dh) 10 ns (1) f s is the sampling frequency. figure 23. audio interface timing (slave mode) 18 submit documentation feedback t (bch) data t (bcl) t (lb) t (bcy) t (bl) t (dh) t (ds) 50% of v cc1 50% of v cc1 50% of v cc1 lrck (input) bck (input) t0010-01 www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 parameters symbol min max unit scki pulse cycle time t (scy) 1/(256 f s ) (1) lrck edge from scki rising edge t (dl) 0 40 ns bck edge from scki rising edge t (db) 0 40 ns bck pulse cycle time t (bcy) 1/(64 f s ) (1) bck high-level time t (bch) 146 ns bck low-level time t (bcl) 146 ns data setup time t (ds) 10 ns data hold time t (dh) 10 ns (1) f s is up to 48 khz. f s is the sampling frequency. figure 24. audio interface timing (master mode) 19 submit documentation feedback t (dl) t (bcy) t (scy) t (ds) 50% of v cc1 lrck (output) 50% of v cc1 50% of v cc1 50% of v cc1 scki bck (output) data t (dh) t (bch) t (bcl) t (db) t (db) t0011-01 www.ti.com
hardware control (pcm1773) pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the digital functions of the pcm1773 device are capable of hardware control. table 3 shows selectable formats, table 4 shows de-emphasis control, and table 5 shows analog mixing control. table 3. data format select fmt data format low 16- to 24-bit, left-justified format high 16- to 24-bit, i 2 s format table 4. de-emphasis control demp de-emphasis function low 44.1-khz de-emphasis off high 44.1-khz de-emphasis on table 5. analog mixing control amix analog mixing low analog mixing off high analog mixing on 20 submit documentation feedback www.ti.com
software control (pcm1772) register write operation (pcm1772) pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the pcm1772 device has many programmable functions that can be controlled in the software control mode. the functions are controlled by programming the internal registers using ms, mc, and md. the software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. the serial control interface is used to program the on-chip mode registers. md is the serial data input, used to program the mode registers. mc is the serial bit clock, used to shift data into the control port. ms is the mode control port select signal. all write operations for the serial control port use 16-bit data words. figure 25 shows the control data word format. the most significant bit must be 0. seven bits, labeled idx[6:0], set the register index (or address) for the write operation. the eight least significant bits, d[7:0], contain the data to be written to the register specified by idx[6:0]. figure 26 shows the functional timing diagram for writing to the serial control port. to write data into the mode register, data is clocked into an internal shift register on the rising edge of the mc clock. serial data can change on the falling edge of the mc clock and must be stable on the rising edge of the mc clock. the ms signal must be low during the write mode, and the rising edge of the ms signal must be aligned with the falling edge of the last mc clock pulse in the 16-bit frame. the mc clock can run continuously between transactions while the ms signal is low. figure 25. control data word format for md figure 26. register write operation 21 submit documentation feedback www.ti.com msb 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 d7 d6 d5 d4 d3 d2 d1 d0 00 lsb register index (or address) register data r0001-01 mc ms md 16 bits (1) single w rite operation msb lsb msb (2) continuous w rite operation msb lsb msb lsb msb lsb 16 bits x n frames mc ms md n frames t0012-01
control interface timing requirements (pcm1772) pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 figure 27 shows a detailed timing diagram for the serial control interface. these timing parameters are critical for proper control port operation. parameters symbol min typ max unit mc pulse cycle time t (mcy) 100 (1) ns mc low-level time t (mcl) 50 ns mc high-level time t (mch) 50 ns ms high-level time t (mhh) (2) ns ms falling edge to mc rising edge t (mls) 20 ns ms hold time t (mlh) 20 ns md hold time t (mdh) 15 ns md setup time t (mds) 20 ns (1) when mc runs continuously between transactions, mc pulse cycle time is specified as 3/(128 f s ), where f s is the sampling rate. (2) 3/(128f s ) s (minimum), where f s is sampling rate figure 27. control interface timing 22 submit documentation feedback www.ti.com t (mch) 50% of v cc1 ms t (mls) lsb 50% of v cc1 50% of v cc1 t (mcl) t (mhh) t (mlh) t (mcy) t (mdh) t (mds) mcmd t0013-01
mode control registers (pcm1772) user-programmable mode controls register map pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the pcm1772 device has a number of user-programmable functions that can be accessed via mode control registers. the registers are programmed using the serial control interface, as discussed in the software control (pcm1772) section. table 6 lists the available mode control functions, along with their reset default conditions and associated register index. table 7 shows the mode control register map. each register includes an index (or address) indicated by the idx[6:0] bits. table 6. user-programmable mode controls function reset default register no. bit(s) soft mute control, l/r independently disabled 01 mutl, mutr digital attenuation level setting, 0 db to ?62 db in 1-db steps, l/r 0 db 01, 02 atl[5:0], atr[5:0] independently oversampling rate control (128 f s , 192 f s , 256 f s , 384 f s ) 128 f s oversampling 03 over polarity control for analog output for r-channel dac not inverted 03 rinv analog mixing control for analog in, ain (terminal 14) disabled 03 amix 44.1-khz de-emphasis control disabled 03 dem audio data format select 24-bit, left-justified format 03 fmt[2:0] zero cross attenuation disabled 04 zcat power-down control disabled 04 pwrd table 7. mode control register map register idx b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 [6:0] (b14- b8) register 01 01h 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 mutr mutl atl5 atl4 atl3 atl2 atl1 atl0 register 02 02h 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 rsv (1) rsv (1) atr5 atr4 atr3 atr2 atr1 atr0 register 03 03h 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 over rsv (1) rinv amix dem fmt2 fmt1 fmt0 register 04 04h 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 rsv (1) rsv (1) rsv (1) zcat rsv (1) rsv (1) rsv (1) pwrd (1) rsv: reserved for test operation. it must be set to 0 during regular operation. 23 submit documentation feedback www.ti.com
register definitions pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 register 01 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 mutr mutl atl5 atl4 atl3 atl2 atl1 atl0 idx[6:0]: 000 0001b mutx: soft mute control where, x = l or r, corresponding to the line output v out l or v out r. default value: 0 mutl, mutr = 0 mute disabled (default) mutl, mutr = 1 mute enabled the mute bits, mutl and mutr, enable or disable the soft mute function for the corresponding line outputs, v out l and v out r. the soft mute function is incorporated into the digital attenuators. when mute is disabled (mutx = 0), the attenuator and dac operate normally. when mute is enabled by setting mutx = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (1 db) at a time. this provides pop-free muting of the line output. by setting mutx = 0, the attenuator is increased one step at a time to the previously programmed attenuation level. atl[5:0]: digital attenuation level setting for line output, v out l default value: 11 1111b line output, v out l, includes a digital attenuation function. the attenuation level can be set from 0 db to ?62 db, in 1-db steps. changes in attenuator levels are made by incrementing or decrementing by one step (1 db) for every 8/f s time internal until the programmed attenuator setting is reached. alternatively, the attenuation level can be set to infinite attenuation (or mute). the following table shows attenuation levels for various settings: atl[5:0] attenuation level setting 11 1111b 0 db, no attenuation (default) 11 1110b ?1 db 11 1101b ?2 db : : 00 0010b ?61 db 00 0001b ?62 db 00 0000b mute register 02 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 rsv rsv atr5 atr4 atr3 atr2 atr1 atr0 idx[6:0]: 000 0010b atr[5:0]: digital attenuation level setting for line output, v out r default value: 11 1111b line output, v out r, includes a digital attenuation function. the attenuation level can be set from 0 db to ?62 db, in 1-db steps. changes in attenuator levels are made by incrementing or decrementing by one step (1 db) for every 8/f s time internal until the programmed attenuator setting is reached. alternatively, the attenuation level can be set to infinite attenuation (or mute). to set the attenuation levels for atr[5:0], see the table for atl[5:0], register 01. 24 submit documentation feedback www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 register 03 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 over rsv rinv amix dem fmt2 fmt1 fmt0 idx[6:0]: 000 0011b over: oversampling control default value: 0 over = 0 128f s oversampling over = 1 192f s , 256f s , 384f s oversampling the over bit controls the oversampling rate of the d - s d/a converters. when it operates at a low sampling rate, less than 24 khz, this function is recommended. rinv: polarity control for line output, v out r default value: 0 rinv = 0 not inverted rinv = 1 inverted output the rinv bits allow the user to control the polarity of the line output, v out r. this function can be used to connect the monaural speaker with btl connection method. this bit is recommended to be 0 during the power-up/-down sequence for minimizing audible pop noise. amix: analog mixing control for external analog signal, ain default value: 0 amix = 0 disabled (not mixed) amix = 1 enabled (mixing to the dac output) amix bit allows the user to mix analog input (ain) with line outputs (v out l/v out r) internally. dem: 44.1-khz de-emphasis control default value: 0 dem = 0 disabled dem = 1 enabled the dem bit enables or disables the digital de-emphasis filter for 44.1-khz sampling rate. fmt[2:0]: audio interface data format default value: 000 the fmt[2:0] bits select the data format for the serial audio interface. the following table shows the available format options. fmt[2:0] audio data format selection 000 16- to 24-bit, left-justified format (default) 001 16- to 24-bit, i 2 s format 010 24-bit right-justified data 011 20-bit right-justified data 100 16-bit right-justified data 101 16- to 24-bit, left-justified format, master mode 110 reserved 111 reserved 25 submit documentation feedback www.ti.com
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 register 04 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 idx6 idx5 idx4 idx3 idx2 idx1 idx0 rsv rsv rsv zcat rsv rsv rsv pwrd idx[6:0]: 000 0100b zcat: zero cross attenuation default value: 0 zcat = 0 normal attenuation (default) zcat = 1 zero cross attenuation this bit enables changing the signal level on zero crossing during attenuation control or muting. if the signal does not cross bpz beyond 512/f s (11.6 ms at the 44.1-khz sampling rate), the signal level is changed similarly to normal attenuation control. this function is independently monitored for each channel; moreover, change of signal level is alternated between both channels. figure 28 shows an example of zero cross attenuation. figure 28. example of zero cross attenuation pwrd: power down control default value: 0 pwrd = 0 normal operation (default) pwrd = 1 power-down state this bit is used to enter into low-power mode. note that pwrd has no reset function. when this bit is set to 1, the pcm1772 device enters low-power mode, and all digital circuits are reset except the register states, which remain unchanged. 26 submit documentation feedback www.ti.com a tt ctrl st art level change point l-channel (1.5 khz) r-channel (1 khz) w0001-01
analog in/out line output (stereo) monaural output (btl mode/monaural speaker) analog input v com output pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 the pcm1772 and pcm1773 devices have two independent lineout amplifiers, and each amplifier output is provided at the corresponding v out l or v out r terminal. the capability of line output is designed for driving a 10-k w minimum load. when the user needs monaural output, the pcm1772 device can provide it. the pcm1772 device has rinv bit on control register 03. because this bit allows the user to invert the polarity of the line output for the right channel, the user can create a monaural output by summing the line output for left and right channels through the external power amplifier or headphone amplifier. the rinv bit is recommended to be 0 during power-up/-down sequence for minimizing audible pop noise. the pcm1772 and pcm1773 devices have an analog input, ain (terminal 10). the amix bit (pcm1772) or the amix terminal (pcm1773) allows the user to mix ain with the line outputs (v out l and v out r) internally. when in mixing mode, an ac-coupling capacitor is needed for ain. but if ain is not used, ain must be open and the amix bit (pcm1772) must be disabled or the amix terminal (pcm1773) must be low. because ain does not have an internal low-pass filter, it is recommended that the bandwidth of the input signal into ain is limited to less than 100 khz. the source of signals connected to ain must be connected by low impedance. although the maximum input voltage on ain is designed to be as large as 0.584 v cc2 [peak-to-peak], the user must attenuate the input voltage on ain and control the digital input data so that each line output (v out l and v out r) does not exceed 0.75 v cc2 [peak-to-peak] during mixing mode. one unbuffered common-mode voltage output terminal, v com, is brought out for decoupling purposes. this terminal is nominally biased to a dc voltage level equal to 0.5 v cc2 and connected to a 10- m f capacitor. in the case of a capacitor smaller than 10 m f, pop noise can be generated during the power-on/-off or power-up/-down sequences. 27 submit documentation feedback www.ti.com
application information connection diagrams power supplies and grounding pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 figure 29 shows the basic connection diagram with the necessary power supply bypassing and decoupling components. it is recommended that the component values shown in figure 29 be used for all designs. the use of series resistors (22 w to 100 w ) is recommended for the scki, lrck, bck, and data inputs. the series resistor combines with the stray pcb and device input capacitance to form a low-pass filter that reduces high-frequency noise emissions and helps to dampen glitches and ringing present on the clock and data lines. the pcm1772 and pcm1773 devices require a 2.4-v typical analog supply for v cc1 and v cc2 . these 2.4-v supplies power the dac, analog output filter, and other circuits. for best performance, these 2.4-v supplies must be derived from the analog supply using a linear regulator, as shown in figure 29 . figure 29 shows the proper power supply bypassing. the 10- m f capacitors must be tantalum or aluminum electrolytic, while the 0.1- m f capacitors are ceramic (x7r type is recommended for surface-mount applications). figure 29. basic connection diagram 28 submit documentation feedback www.ti.com lrck 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 pcm1772 data bck pd agnd1agnd2 v com v out r scki v out l ms mcmd v cc1 ain v cc2 controller analog in post lpf audio dsp power amplifieror headphone amplifier 10 m f post lpf power amplifieror headphone amplifier 10 m f s0007-01 10 m f 1.6 v to 3.6 v 10 m f 10 m f 0.1 m f 10 m f 0.1 m f
pcm1772 , pcm1773 sles010g ? september 2001 ? revised march 2007 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from f revision (november 2005) to g revision .......................................................................................... page changed signal name from mcki to scki ......................................................................................................................... 28 corrected errors, added recommended parts, and changed incorrect symbols ................................................................ 28 changes from e revision (april 2005) to f revision .................................................................................................... page changed dynamic performance for full-scale output voltage of line output from 0.75 vcc2 to 0.77 vcc2 ........................... 3 changes from d revision (may 2004) to e revision ..................................................................................................... page changed data sheet to new format ...................................................................................................................................... 1 changed value for power-supply voltage ............................................................................................................................. 2 removed package/ordering information, reformatted, and appended at end of data sheet ................................................ 2 added new recommended operating conditions table to data sheet ................................................................................. 2 changed page layout for terminal function tables ................................................................................................................ 5 changed page layout of figure 13 and figure 14 .............................................................................................................. 11 in figure 22 , added arrows to all rising edges of bck for data formats (2), (3), and (4) ................................................... 17 in figure 29 , changed signal direction on scki pin ........................................................................................................... 28 29 submit documentation feedback www.ti.com
package option addendum www.ti.com 24-apr-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pcm1772pw active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1772 PCM1772PWG4 active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1772 pcm1772pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1772 pcm1772pwrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1772 pcm1772rga active vqfn rga 20 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 1772 pcm1772rgar active vqfn rga 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 1772 pcm1773pw active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1773 pcm1773pwg4 active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1773 pcm1773pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 1773 pcm1773rga active vqfn rga 20 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 1773 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material)
package option addendum www.ti.com 24-apr-2015 addendum-page 2 (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant pcm1772pwr tssop pw 16 2000 330.0 17.4 6.8 5.4 1.6 8.0 16.0 q1 pcm1772rgar vqfn rga 20 2000 330.0 13.4 4.4 4.4 1.3 8.0 12.0 q1 pcm1773pwr tssop pw 16 2000 330.0 17.4 6.8 5.4 1.6 8.0 16.0 q1 package materials information www.ti.com 16-jul-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) pcm1772pwr tssop pw 16 2000 367.0 367.0 38.0 pcm1772rgar vqfn rga 20 2000 367.0 367.0 35.0 pcm1773pwr tssop pw 16 2000 367.0 367.0 38.0 package materials information www.ti.com 16-jul-2016 pack materials-page 2

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